To begin with, it should be noted that the terms “sigma-delta modulator (SDM)” and “sigma-delta converter” are used interchangeably below. In terms of hardware, an SD AD converter comprises a modulator with a downstream digital filter.
Basic details of the prior art of sigma-delta modulators can be found in: Norsworthy, S. R.; Schreiber, R.; Temes, G. C.: Delta-Sigma Data Converters: Theory, Design, and Simulation.—IEEE, November 1996 (ISBN: 0780310454).
Sigma-delta modulators form the basis of the AD converters which are preferably used in wire-based and wire-free communication. The trend towards increasingly more advanced digital signal processing and, as a result thereof, towards AD conversion as close to the input or antenna as possible means that there is a need for converters having an ever higher resolution and wider bandwidth.
The object of providing converters having a wide bandwidth and high resolution in conjunction with a simultaneously moderate power consumption therefore arises for mobile applications.
There are, in principle, three ways of increasing the resolution of sigma-delta modulators:                by increasing the resolution of the quantizer (more bits)—this is associated with linearity problems on account of element mismatch;        by raising the order and/or Q-factor of the filters in the modulator—this is associated with stability problems;        by increasing oversampling—in this case, the power loss increases with at least the square of the clock frequency. In addition, the requirements imposed on the maximum permissible clock jitter become more stringent as the clock frequency increases.        
There are two customary SDM embodiments in the prior art:                a) Discrete-time converters based on switched-capacitor technology. The input signal is sampled at the SDM's input. This embodiment is resistant to parameter fluctuations, not very sensitive to clock jitter and is therefore the most common embodiment. Its fundamental disadvantage is the need to select the bandwidth of the operational amplifiers such that it is at least five times to ten times the magnitude of the clock frequency. In addition, the capacitor reset noise (kTC noise) predetermines a minimum size for the capacitors used. As a result, these converters increasingly draw a very large amount of current at high clock frequencies of above approximately 50 MHz and/or high resolutions (above approximately 16 bits). Sampling at the SDM's input requires additional input filters in order to avoid aliasing, said input filters occupying an even larger area and further increasing the power consumption. They therefore do not constitute a suitable solution for mobile applications having a high resolution and wide bandwidth.        b) Converters based on continuous-time integrators. The integrators are usually implemented using RC, IC or gmC technology. These converters are sensitive to parameter fluctuations which affect the time constant. However, their fundamental disadvantage in customary embodiments is the considerably higher jitter sensitivity than SC solutions. The reason for this is integration via the feedback signal, so that the time integral via the signal which has been fed back (generally a current) determines the circuit's response. As a result, the clock jitter directly affects the feedback signal. Since the amplitude of the feedback signal is, in general, considerably higher than the amplitude of the input signal, the jitter sensitivity is increased further as a result. These continuous-time converters are thus suitable for higher clock rates, since the bandwidth of the operational amplifiers has to correspond only approximately to the clock frequency in this case. Low-pass filtering of the input signal is generally carried out together with noise shaping in the same filter blocks within the SD modulator, so that an anti-aliasing input filter is not usually required.        c) In accordance with a new proposal by Prof. Hernandez, University of Madrid, it is also possible to implement SDMs based on delay lines instead of integrators. Although, conceptually, this provides a good compromise between speed (since time-continuous) and jitter sensitivity, suitable continuous-time delay lines cannot, in practice, be integrated in silicon ICs. Customary and suitable separate delay lines are based on SAW, BAW or distributed LC concepts. All of these embodiments have a very low impedance (typically 50 to 200 ohm), again giving rise to a high power consumption. Therefore, neither does this interesting concept constitute a practical solution for the requirements mentioned.        